From: lkcl <lkcl@web>
Date: Mon, 13 Jun 2022 16:37:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1810
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0cfe40ee7097a127d7398e7e20f4de9e1a2451f8;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 0f6132b08..805c42deb 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -101,9 +101,11 @@ an Exception or Interrupt may not occur during the pair of Moves.
 **SVP64 Vectorised**
 
 Vectorised Swizzle may be considered to be an extended static predicate
-mask for subvectors (SUBVL=2/3/4). SUBVL (and SRC_SUBVL, see later section)
-must be set in order to aid in determining source and destination subvector
-lengths.
+mask for subvectors (SUBVL=2/3/4). Due to the skipping caused by
+the static predication capability, the destination
+subvector length can be *different* from the source subvector
+length, and consequently the destination subvector length is
+encoded into the Swizzle.
 
 When Vectorised, given the use-case is for a High-performance GPU,
 the fundamental assumption is that Micro-coding or
@@ -168,6 +170,12 @@ each destination position, the marker "0b001" may be used to indicate
 the end. If no marker is present then the destination subvector length
 may be assimed to be 4.
 
+To determine the value to be copied from the source:
+```
+def get_src_from_dest(swiz, idx):
+    
+```
+
 # RM Mode Concept:
 
 MVRM-2P-1S1D: