From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 18:23:31 +0000 (-0700)
Subject: Merge branch 'master' into mwk/xilinx_bufgmap
X-Git-Tag: working-ls180~1097^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d0ad158984ddc3f66f895b6c18a62f250d2248e;p=yosys.git

Merge branch 'master' into mwk/xilinx_bufgmap
---

0d0ad158984ddc3f66f895b6c18a62f250d2248e
diff --cc techlibs/xilinx/cells_sim.v
index 26df5bc93,e3897d9a6..f1e019d1e
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -313,9 -300,11 +315,12 @@@ endmodul
  (* abc_box_id = 5 *)
  module RAM32X1D (
    output DPO, SPO,
-   (* abc_scc_break *) input D,
-   (* clkbuf_sink *) input  WCLK,
-   (* abc_scc_break *) input WE,
+   (* abc_scc_break *)
+   input  D,
++  (* clkbuf_sink *)
+   input  WCLK,
+   (* abc_scc_break *)
+   input  WE,
    input  A0, A1, A2, A3, A4,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
  );
@@@ -333,9 -322,10 +338,12 @@@ endmodul
  (* abc_box_id = 6 *)
  module RAM64X1D (
    output DPO, SPO,
-   (* abc_scc_break *) input D,
-   (* clkbuf_sink *) input  WCLK,
-   (* abc_scc_break *) input WE,
+   (* abc_scc_break *)
+   input  D,
++  (* clkbuf_sink *)
+   input  WCLK,
 -  (* abc_scc_break *) input WE,
++  (* abc_scc_break *)
++  input WE,
    input  A0, A1, A2, A3, A4, A5,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
  );
@@@ -353,9 -343,11 +361,12 @@@ endmodul
  (* abc_box_id = 7 *)
  module RAM128X1D (
    output       DPO, SPO,
-   (* abc_scc_break *) input D,
-   (* clkbuf_sink *) input WCLK,
-   (* abc_scc_break *) input WE,
+   (* abc_scc_break *)
+   input        D,
++  (* clkbuf_sink *)
+   input        WCLK,
+   (* abc_scc_break *)
+   input        WE,
    input  [6:0] A, DPRA
  );
    parameter INIT = 128'h0;