From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Jul 2020 12:52:38 +0000 (+0100)
Subject: get/set slow spr in spr test_pipe_caller
X-Git-Tag: div_pipeline~162^2~62
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d187ed15e4997f9b3dc28b5451ecf68733390c0;p=soc.git

get/set slow spr in spr test_pipe_caller
---

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index 77d0519a..e5da4042 100644
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -25,7 +25,8 @@ def get_cu_inputs(dec2, sim):
 
     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
-    yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR1
+    yield from ALUHelpers.get_sim_slow_spr1(res, sim, dec2) # FAST1
+    yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # FAST1
     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
     yield from ALUHelpers.get_sim_xer_ov(res, sim, dec2) # XER.ov
     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
@@ -47,8 +48,8 @@ def set_alu_inputs(alu, dec2, sim):
     yield from ALUHelpers.set_xer_ov(alu, dec2, inp)
     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
 
-    # XXX TODO slow spr1
     yield from ALUHelpers.set_fast_spr1(alu, dec2, inp)
+    yield from ALUHelpers.set_slow_spr1(alu, dec2, inp)
 
 
 # This test bench is a bit different than is usual. Initially when I
@@ -197,6 +198,7 @@ class TestRunner(FHDLTestCase):
 
         yield from ALUHelpers.get_int_o(res, alu, dec2)
         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
+        yield from ALUHelpers.get_slow_spr1(res, alu, dec2)
         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
         yield from ALUHelpers.get_xer_so(res, alu, dec2)
@@ -208,11 +210,13 @@ class TestRunner(FHDLTestCase):
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
 
         ALUHelpers.check_xer_ov(self, res, sim_o, code)
         ALUHelpers.check_xer_ca(self, res, sim_o, code)
         ALUHelpers.check_int_o(self, res, sim_o, code)
         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
+        ALUHelpers.check_slow_spr1(self, res, sim_o, code)
         ALUHelpers.check_xer_so(self, res, sim_o, code)
 
 
diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 85ad2e14..519e1108 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -44,6 +44,13 @@ class ALUHelpers:
     def get_sim_msr(res, sim, dec2):
         res['msr'] = sim.msr.value
 
+    def get_sim_slow_spr1(res, sim, dec2):
+        spr1_en = yield dec2.e.read_spr1.ok
+        if spr1_en:
+            spr1_sel = yield dec2.e.read_spr1.data
+            spr1_data = sim.spr[spr1_sel].value
+            res['spr1'] = spr1_data
+
     def get_sim_fast_spr1(res, sim, dec2):
         fast1_en = yield dec2.e.read_fast1.ok
         if fast1_en:
@@ -272,6 +279,13 @@ class ALUHelpers:
             spr_name = spr_dict[spr_num].SPR
             res['fast1'] = sim.spr[spr_name].value
 
+    def get_wr_slow_spr1(res, sim, dec2):
+        ok = yield dec2.e.write_spr.ok
+        if ok:
+            spr_num = yield dec2.e.write_spr.data
+            spr_name = spr_dict[spr_num].SPR
+            res['spr1'] = sim.spr[spr_name].value
+
     def get_wr_sim_xer_ca(res, sim, dec2):
         cry_out = yield dec2.e.output_carry
         if cry_out:
@@ -293,6 +307,13 @@ class ALUHelpers:
         if oe and oe_ok:
             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 
+    def check_slow_spr1(dut, res, sim_o, msg):
+        if 'spr1' in res:
+            expected = sim_o['spr1']
+            alu_out = res['spr1']
+            print(f"expected {expected:x}, actual: {alu_out:x}")
+            dut.assertEqual(expected, alu_out, msg)
+
     def check_fast_spr1(dut, res, sim_o, msg):
         if 'fast1' in res:
             expected = sim_o['fast1']