From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Dec 2019 07:04:40 +0000 (-0800)
Subject: Missing wire declaration
X-Git-Tag: working-ls180~881^2^2~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d248dd7bae707505071b309b55bac75facccab8;p=yosys.git

Missing wire declaration
---

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 3fa5f5a1c..d2159f82d 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -192,6 +192,7 @@ module FDCE (output Q, input C, CE, D, CLR);
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
+  wire QQ, $nextQ, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDPE_1 #(