From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 26 Apr 2016 17:49:05 +0000 (+0200)
Subject: Connections between inputs and inouts are driven by the input
X-Git-Tag: yosys-0.7~240
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d2923cccd00ed14537f3239b0059a76673798a4;p=yosys.git

Connections between inputs and inouts are driven by the input
---

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 466808216..6600ffa25 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -156,6 +156,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
 	if (w1->port_input != w2->port_input)
 		return w2->port_input;
 
+	if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
+		return !(w2->port_input && w2->port_output);
+
 	if (w1->name[0] == '\\' && w2->name[0] == '\\') {
 		if (regs.check_any(s1) != regs.check_any(s2))
 			return regs.check_any(s2);