From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 25 May 2015 11:55:15 +0000 (+0200)
Subject: litesata/core/link: move buffer on CONTInserter (seems better for timings when set... 
X-Git-Tag: 24jan2021_ls180~2247
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d2db236038b6095064332018be946bab5834461;p=litex.git

litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)
---

diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py
index a723112e..f6553a0d 100644
--- a/misoclib/mem/litesata/core/link/__init__.py
+++ b/misoclib/mem/litesata/core/link/__init__.py
@@ -36,7 +36,7 @@ class LiteSATALinkTX(Module):
 
         # inserter CONT and scrambled data between
         # CONT and next primitive
-        cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32)))
+        cont = BufferizeEndpoints("sink")(LiteSATACONTInserter(phy_description(32)))
         self.submodules += cont
 
         # datas / primitives mux