From: lkcl Date: Sat, 25 Mar 2023 20:28:09 +0000 (+0000) Subject: (no commit message) X-Git-Tag: opf_rfc_ls001_v3~65 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d30afa6b69f69f4122f6e636eb1d415615960ef;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn index 3fda6ee30..8e8d6dbbe 100644 --- a/openpower/sv/rfc/ls008.mdwn +++ b/openpower/sv/rfc/ls008.mdwn @@ -266,7 +266,8 @@ mfspr) are 100% guaranteed to have zero impact on SVP64 state. **Max Vector Length (maxvl)** MAXVECTORLENGTH is the same concept as MVL in RISC-V RVV, except that it -is variable length and may be dynamically set. MVL is limited to 7 bits +is variable length and may be dynamically set (normally from an immediate +field only). MVL is limited to 7 bits (in the first version of SVP64) and consequently the maximum number of elements is limited to between 0 and 127. @@ -282,11 +283,12 @@ and allocation and only utilise `setvl`. Direct writing to SVSTATE in order to `setvl` is conceptually similar but different from the Cray, SX Aurora, and RISC-V RVV equivalent. Similar to RVV, VL is set to be within -the range 0 <= VL <= MVL +the range 0 <= VL <= MVL. Unlike RVV, VL is set **exactly** according to the following: - VL = rd = MIN(vlen, MVL) + VL = (RT|0) = MIN(vlen, MVL) -where 0 <= MVL <= XLEN +where 0 <= MVL <= XLEN and vlen may come from an immediate, `RA`, or from the `CTR` SPR, +depending on options set with the `setvl` instruction. **SUBVL - Sub Vector Length** @@ -297,7 +299,9 @@ operation issued, SUBVL operations are issued. The main effect of SUBVL is that predication bits are applied per **group**, rather than by individual element. Legal values are 0 to 3, -representing 1 operation thru 4 operations respectively. +representing 1 operation (1 element) thru 4 operations (4 elements) respectively. +Elements are best though of in the context of 3D, Audio and Video: two Left and Right +Channel "elements" or four ARGB "elements", or three XYZ coordinate "elements". **Horizontal Parallelism**