From: Luke Kenneth Casson Leighton Date: Fri, 29 May 2020 15:49:29 +0000 (+0100) Subject: trigger read ALU ready/valid from latch as well X-Git-Tag: div_pipeline~743 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d31c83eb1089bb9f9974465b1e9b51d65b8b339;p=soc.git trigger read ALU ready/valid from latch as well --- diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index cf3cf0ba..baa18031 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -286,9 +286,10 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # on a go_read, tell the ALU we're accepting data. # NOTE: this spells TROUBLE if the ALU isn't ready! # go_read is only valid for one clock! - with m.If(all_rd): # src operands ready, GO! - with m.If(~self.alu.p.ready_o): # no ACK yet - m.d.comb += self.alu.p.valid_i.eq(1) # so indicate valid + m.submodules.alui_l = alui_l = SRLatch(False, name="alui") + m.d.comb += self.alu.p.valid_i.eq(alui_l.q) + m.d.comb += alui_l.r.eq(self.alu.p.ready_o) # valid for one extra + m.d.comb += alui_l.s.eq(all_rd_pulse) # ALU output "ready" side. alu "ready" indication stays hi until # ALU says "valid". diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index 1be45181..c765af1d 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -44,7 +44,7 @@ def get_cu_output(cu, idx): yield yield cu.wr.go[idx].eq(1) yield - result = yield cu.dst_i[idx] + result = yield cu.dest[idx] yield cu.wr.go[idx].eq(0) return result