From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 16 Apr 2015 09:30:56 +0000 (+0200)
Subject: improved ice40 dff cell mapping
X-Git-Tag: yosys-0.6~329
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d344a23d36fba06cc1032e8754c70ad5c1f4b15;p=yosys.git

improved ice40 dff cell mapping
---

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index f7008a571..0227ffadb 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -1,6 +1,31 @@
-module  \$_DFF_P_ (input D, C, output Q);
-  SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C));
-endmodule
+module  \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); SB_DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
+
+module  \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
+
+module  \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
+
+module  \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
+
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
+
+module  \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
+module  \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
+module  \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
+module  \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
 
 module \$lut (A, Y);
   parameter WIDTH = 0;
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 58e067415..9c63336d7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -70,10 +70,10 @@ endmodule
 // SiliconBlue Logic Cells
 
 module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] INIT = 0;
-	wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
-	wire [3:0] s2 = I2 ?   s3[ 7:4] :   s3[3:0];
-	wire [1:0] s1 = I1 ?   s2[ 3:2] :   s2[1:0];
+	parameter [15:0] LUT_INIT = 0;
+	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
+	wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
+	wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2fe921407..b683929bf 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -69,6 +69,12 @@ struct SynthIce40Pass : public Pass {
 		log("        techmap\n");
 		log("        opt -fast\n");
 		log("\n");
+		log("    map_ffs:\n");
+		log("        dff2dffe -direct-match $_DFF_*\n");
+		log("        techmap -map +/ice40/cells_map.v\n");
+		log("        simplemap\n");
+		log("        clean\n");
+		log("\n");
 		log("    map_luts:\n");
 		log("        abc -lut 4\n");
 		log("        clean\n");
@@ -135,6 +141,14 @@ struct SynthIce40Pass : public Pass {
 			Pass::call(design, "opt -fast");
 		}
 
+		if (check_label(active, run_from, run_to, "map_ffs"))
+		{
+			Pass::call(design, "dff2dffe -direct-match $_DFF_*");
+			Pass::call(design, "techmap -map +/ice40/cells_map.v");
+			Pass::call(design, "simplemap");
+			Pass::call(design, "clean");
+		}
+
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
 			Pass::call(design, "abc -lut 4");