From: Peter Crozier <peter@crozier.com>
Date: Wed, 3 Jun 2020 16:19:28 +0000 (+0100)
Subject: Merge branch 'master' into struct
X-Git-Tag: working-ls180~504^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d3f7ea011288e1a1fadd4ae27f1e8a57d729053;p=yosys.git

Merge branch 'master' into struct
---

0d3f7ea011288e1a1fadd4ae27f1e8a57d729053
diff --cc frontends/verilog/verilog_parser.y
index e72d09524,c8223f41d..c4867356c
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@@ -885,8 -841,31 +885,20 @@@ task_func_port
  		}
  		albuf = $1;
  		astbuf1 = $2;
 -		astbuf2 = $3;
 -		if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
 -			if (astbuf2) {
 -				frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
 -			} else {
 -				astbuf2 = new AstNode(AST_RANGE);
 -				astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
 -				astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
 -			}
 -		}
 -		if (astbuf2 && astbuf2->children.size() != 2)
 -			frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
 +		astbuf2 = checkRange(astbuf1, $3);
- 	} wire_name | wire_name;
+ 	} wire_name |
+ 	{
+ 		if (!astbuf1) {
+ 			if (!sv_mode)
+ 				frontend_verilog_yyerror("task/function argument direction missing");
+ 			albuf = new dict<IdString, AstNode*>;
+ 			astbuf1 = new AstNode(AST_WIRE);
+ 			current_wire_rand = false;
+ 			current_wire_const = false;
+ 			astbuf1->is_input = true;
+ 			astbuf2 = NULL;
+ 		}
+ 	} wire_name;
  
  task_func_body:
  	task_func_body behavioral_stmt |