From: Joel Stanley <joel@jms.id.au>
Date: Tue, 11 May 2021 04:47:26 +0000 (+0930)
Subject: openocd: Fix verify command for v0.10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d4a0bab6e50fbc9879305a75d8f930850dc6cbd;p=microwatt.git

openocd: Fix verify command for v0.10

v0.11 uses verify_image, which is not supported by v0.11. Use the old
verify_bank for v0.10.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---

diff --git a/openocd/flash-arty b/openocd/flash-arty
index 5cb534d..815dea9 100755
--- a/openocd/flash-arty
+++ b/openocd/flash-arty
@@ -6,7 +6,6 @@ import subprocess
 import sys
 
 BASE = os.path.dirname(os.path.abspath(__file__))
-CONFIG = os.path.join(BASE, "xilinx-xc7.cfg")
 
 def flash(config, flash_proxy, address, data, filetype="", set_qe=False):
     script = "; ".join([
@@ -49,5 +48,6 @@ else:
     sys.exit()
 
 proxy = os.path.join(BASE, proxy)
+config = os.path.join(BASE, "xilinx-xc7{}.cfg".format(version))
 
-flash(CONFIG, proxy, args.address, args.file, args.filetype.lower())
+flash(config, proxy, args.address, args.file, args.filetype.lower())
diff --git a/openocd/xilinx-xc7.cfg b/openocd/xilinx-xc7.cfg
index 8824ccf..5359d4f 100644
--- a/openocd/xilinx-xc7.cfg
+++ b/openocd/xilinx-xc7.cfg
@@ -51,10 +51,10 @@ proc jtagspi_program {bin addr {type ""} } {
 	global _FLASHNAME
 	if { $type eq "" } {
 		flash write_image erase $bin $addr
-		flash verify_image $bin $addr
+		flash verify_bank $_FLASHNAME $bin $addr
 	} else {
 		flash write_image erase $bin $addr $type
-		flash verify_image $bin $addr $type
+		flash verify_bank $_FLASHNAME $bin $addr $type
 	}
 }
 # end jtagspi.cfg
diff --git a/openocd/xilinx-xc7_openocd_v0.11.cfg b/openocd/xilinx-xc7_openocd_v0.11.cfg
new file mode 100644
index 0000000..8f7df34
--- /dev/null
+++ b/openocd/xilinx-xc7_openocd_v0.11.cfg
@@ -0,0 +1,68 @@
+# This file is the same sa xilinx-xc7.cfg, except we use
+# verify_image instead of verify_bank
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+ftdi_channel 0
+ftdi_layout_init 0x00e8 0x60eb
+reset_config none
+adapter_khz 25000
+
+source [find cpld/xilinx-xc7.cfg]
+
+# From jtagspi.cfg with modification to support
+# specifying file type
+set _USER1 0x02
+
+if { [info exists JTAGSPI_IR] } {
+	set _JTAGSPI_IR $JTAGSPI_IR
+} else {
+	set _JTAGSPI_IR $_USER1
+}
+
+if { [info exists DR_LENGTH] } {
+	set _DR_LENGTH $DR_LENGTH
+} else {
+	set _DR_LENGTH 1
+}
+
+if { [info exists TARGETNAME] } {
+	set _TARGETNAME $TARGETNAME
+} else {
+	set _TARGETNAME $_CHIPNAME.proxy
+}
+
+if { [info exists FLASHNAME] } {
+	set _FLASHNAME $FLASHNAME
+} else {
+	set _FLASHNAME $_CHIPNAME.spi
+}
+
+target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
+flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
+
+proc jtagspi_init {chain_id proxy_bit} {
+	# load proxy bitstream $proxy_bit and probe spi flash
+	global _FLASHNAME
+	pld load $chain_id $proxy_bit
+	reset halt
+	flash probe $_FLASHNAME
+}
+
+proc jtagspi_program {bin addr {type ""} } {
+	# write and verify binary file $bin at offset $addr
+	global _FLASHNAME
+	if { $type eq "" } {
+		flash write_image erase $bin $addr
+		flash verify_image $bin $addr
+	} else {
+		flash write_image erase $bin $addr $type
+		flash verify_image $bin $addr $type
+	}
+}
+# end jtagspi.cfg
+
+proc fpga_program {} {
+    global _CHIPNAME
+    xc7_program $_CHIPNAME.tap
+}