From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 8 Feb 2016 01:05:21 +0000 (-0800)
Subject: Set default RV32 RAM size to 4 GiB - 256 MiB
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d5bd9e810db2f2eafaed3de472ac1130501fd41;p=riscv-isa-sim.git

Set default RV32 RAM size to 4 GiB - 256 MiB

This allows, by default, 256 MiB of addressable I/O space.
---

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 67b655e..69d5e19 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -30,11 +30,11 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
   size_t memsz0 = (size_t)mem_mb << 20;
   size_t quantum = 1L << 20;
   if (memsz0 == 0)
-    memsz0 = 1L << (sizeof(size_t) == 8 ? 32 : 30);
+    memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
 
   memsz = memsz0;
   while ((mem = (char*)calloc(1, memsz)) == NULL)
-    memsz = memsz*10/11/quantum*quantum;
+    memsz = (size_t)(memsz*0.9)/quantum*quantum;
 
   if (memsz != memsz0)
     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",