From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 13 Oct 2007 03:08:12 +0000 (-0700)
Subject: X86: Added some new versions of MOV and a new argument type tag.
X-Git-Tag: m5_2.0_beta4~55^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d6383b69e75dc9e5b3c9b45a62f5a472657fa85;p=gem5.git

X86: Added some new versions of MOV and a new argument type tag.

--HG--
extra : convert_revision : e21b2062d68baa983c7c631b3e1fe3149de56427
---

diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index aed7fb7e7..da7867401 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -325,17 +325,17 @@
                 default: lahf();
             }
         }
-        0x14: decode OPCODE_OP_BOTTOM3 {
-            0x0: mov_Al_Ob();
-            0x1: mov_rAX_Ov();
-            0x2: mov_Ob_Al();
-            0x3: mov_Ov_rAX();
-            0x4: StringInst::MOVS(Yb,Xb);
-            0x5: StringInst::MOVS(Yv,Xv);
-            0x6: StringTestInst::CMPS(Yb,Xb);
-            0x7: StringTestInst::CMPS(Yv,Xv);
-        }
         format Inst {
+            0x14: decode OPCODE_OP_BOTTOM3 {
+                0x0: MOV(rAb, Ob);
+                0x1: MOV(rAv, Ov);
+                0x2: MOV(Ob, rAb);
+                0x3: MOV(Ov, rAv);
+                0x4: StringInst::MOVS(Yb,Xb);
+                0x5: StringInst::MOVS(Yv,Xv);
+                0x6: StringTestInst::CMPS(Yb,Xb);
+                0x7: StringTestInst::CMPS(Yv,Xv);
+            }
             0x15: decode OPCODE_OP_BOTTOM3 {
                 0x0: TEST(rAb,Ib);
                 0x1: TEST(rAv,Iz);
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index a248f5656..04f9ea12a 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -59,6 +59,16 @@ microcode = '''
 # Regular moves
 #
 
+def macroop MOV_R_MI {
+    limm t1, imm
+    ld reg, seg, [1, t0, t1]
+};
+
+def macroop MOV_MI_R {
+    limm t1, imm
+    st reg, seg, [1, t0, t1]
+};
+
 def macroop MOV_R_R {
     mov reg, reg, regm
 };
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 59e9577d9..cf6b6ff86 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -172,6 +172,9 @@ let {{
             elif opType.tag in ("I", "J"):
                 # Immediates
                 Name += "_I"
+            elif opType.tag == "O":
+                # Immediate containing a memory offset
+                Name += "_MI"
             elif opType.tag in ("PR", "R", "VR"):
                 # Non register modrm settings should cause an error
                 env.addReg(ModRMRMIndex)