From: Jakub Jelinek Date: Fri, 10 Jan 2014 21:27:52 +0000 (+0100) Subject: re PR rtl-optimization/59754 ([ree.c] Incorrect merge while working with vector regis... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d6d7b9a20f3ed4370214a03f1ee26bdda4ad4e9;p=gcc.git re PR rtl-optimization/59754 ([ree.c] Incorrect merge while working with vector registers) PR rtl-optimization/59754 * ree.c (combine_reaching_defs): Disallow !SCALAR_INT_MODE_P modes in the REGNO != REGNO case. From-SVN: r206542 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 997cfa710b9..89f60a2ea1f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2014-01-10 Jakub Jelinek + + PR rtl-optimization/59754 + * ree.c (combine_reaching_defs): Disallow !SCALAR_INT_MODE_P + modes in the REGNO != REGNO case. + 2014-01-10 Bill Schmidt * config/rs6000/rs6000-builtin.def: Fix pasto for VPKSDUS. diff --git a/gcc/ree.c b/gcc/ree.c index 1c4f3ad6fa2..01ccd699626 100644 --- a/gcc/ree.c +++ b/gcc/ree.c @@ -702,6 +702,18 @@ combine_reaching_defs (ext_cand *cand, const_rtx set_pat, ext_state *state) if (state->modified[INSN_UID (cand->insn)].kind != EXT_MODIFIED_NONE) return false; + /* Transformation of + (set (reg1) (expression)) + (set (reg2) (any_extend (reg1))) + into + (set (reg2) (any_extend (expression))) + (set (reg1) (reg2)) + is only valid for scalar integral modes, as it relies on the low + subreg of reg1 to have the value of (expression), which is not true + e.g. for vector modes. */ + if (!SCALAR_INT_MODE_P (GET_MODE (SET_DEST (PATTERN (cand->insn))))) + return false; + /* There's only one reaching def. */ rtx def_insn = state->defs_list[0];