From: lkcl <lkcl@web>
Date: Tue, 7 Jun 2022 10:48:32 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1924
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d6f35aa4ccf01785f3360a061934e511f26a4fa;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 7427720a3..846653898 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -60,6 +60,12 @@ Comparative instruction count:
   prerequisite SFS (150) or
   SFFS (214) Compliancy Subsets
 
+SV comprises several [[sv/compliancy_levels]] suited to Embedded, Energy
+efficient High-Performance Compute, Distributed Computing and Advanced
+Computational Supercomputing.  The Compliancy Levels are arranged such
+that even at the bare minimum Level, full Soft-Emulation of all
+optional and future features is possible.
+
 # Major opcodes summary
 
 Please be advised that even though below is entirely DRAFT status, there
@@ -113,6 +119,8 @@ anaemic and out-of-date compared to ARM and x86. Approximately
 Pages being developed and examples
 
 * [[sv/overview]] explaining the basics.
+* [[sv/compliancy_levels]] for minimum subsets through to Advanced
+  Supercomputing.
 * [[sv/implementation]] implementation planning and coordination
 * [[sv/svp64]] contains the packet-format *only*, the [[sv/svp64/appendix]]
   contains explanations and further details