From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 May 2020 19:40:15 +0000 (+0100)
Subject: add TODO
X-Git-Tag: div_pipeline~1169
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d6f97fbc8f73829dbe1045947149b90d058ff1c;p=soc.git

add TODO
---

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index 8b75e5f7..f2a9370c 100644
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -74,16 +74,20 @@ class BranchMainStage(PipeModBase):
         ######## main switch statement ########
 
         with m.Switch(op.insn_type):
+            #### branch ####
             with m.Case(InternalOp.OP_B):
                 li = Signal(i_fields['LI'][0:-1].shape())
                 comb += li.eq(i_fields['LI'][0:-1])
                 comb += br_imm_addr.eq(br_ext(li))
                 comb += br_taken.eq(1)
+            #### branch conditional ####
             with m.Case(InternalOp.OP_BC):
                 bd = Signal(b_fields['BD'][0:-1].shape())
                 comb += bd.eq(b_fields['BD'][0:-1])
                 comb += br_imm_addr.eq(br_ext(bd))
                 comb += br_taken.eq(bc_taken)
+            #### branch conditional reg ####
+            # TODOwith m.Case(InternalOp.OP_BCREG):
 
         ###### output next instruction address #####