From: lkcl Date: Fri, 8 Apr 2022 00:29:18 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2849 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d7ad9e98688d8a8abb0edfb72ce27850634a23a;p=libreriscv.git --- diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 50fca0f39..e7ded9b99 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -199,7 +199,7 @@ Brief description of fields: if VSb is set, VL is truncated if the test succeeds. If VSb is clear, VL is truncated if a test *fails*. Masked-out (skipped) bits are not considered - part of testing. + part of testing when `sz=0` * **CTi** CTR inversion. CTR-test Mode normally decrements per element tested. CTR inversion decrements if a test *fails*. Only relevant in CTR-test Mode. @@ -575,7 +575,7 @@ Below is the pseudocode for SVP64 Branches, which is a little less obvious but identical to the above. The lack of obviousness is down to the early-exit opportunities. -Pseudocode for Horizontal-First Mode: +Effective pseudocode for Horizontal-First Mode: ``` if (mode_is_64bit) then M <- 0 @@ -590,10 +590,10 @@ for srcstep in range(VL): testbit = CRbits[BI & 0b11] # testbit = CR[BI+32+srcstep*4] else if not SVRMmode.sz: - # inverted CTR test skip mode - if ¬BO[2] & CTRtest & ¬CTI then - CTR = CTR - 1 - continue # skip to next element + # inverted CTR test skip mode + if ¬BO[2] & CTRtest & ¬CTI then + CTR = CTR - 1 + continue # skip to next element else testbit = SVRMmode.SNZ # actual element test here