From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 26 Nov 2019 00:07:47 +0000 (-0800)
Subject: Move \init from source wire to submod if output port
X-Git-Tag: working-ls180~778^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d7ba77426b5ede6eae76059d8182ab096041ff2;p=yosys.git

Move \init from source wire to submod if output port
---

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 212932e46..7952c2dd6 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -162,6 +162,13 @@ struct SubmodWorker
 			new_wire->port_input = new_wire_port_input;
 			new_wire->port_output = new_wire_port_output;
 			new_wire->attributes = wire->attributes;
+			if (new_wire->port_output) {
+				auto it = wire->attributes.find(ID(init));
+				if (it != wire->attributes.end()) {
+					new_wire->attributes[ID(init)] = it->second[bit.offset];
+					it->second[bit.offset] = State::Sx;
+				}
+			}
 
 			if (new_wire->port_input && new_wire->port_output)
 				log("  signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());