From: lkcl <lkcl@web>
Date: Mon, 2 May 2022 16:03:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2512
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d7d841675382bd1ab2f473122fa00714cd7ed79;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 8f44c94bb..994d17e4d 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -15,6 +15,14 @@ Table of contents:
 
 [[!toc]]
 
+# Partial Implementations
+
+It is perfectly legal to implement subsets of SVP64 as long as illegal
+instruction traps are always raised on unimplemented features,
+so that soft-emulation is possible,
+even for future revisions of SVP64. With SVP64 being partly controlled
+through contextual SPRs, a little care has to be taken.
+
 # XER, SO and other global flags
 
 Vector systems are expected to be high performance.  This is achieved