From: Richard Sandiford Date: Wed, 7 Aug 2019 19:01:37 +0000 (+0000) Subject: [AArch64] Merge SVE ternary FP operations X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d80d083a2e1d368fcb11eb7ea5490c274f0ea15;p=gcc.git [AArch64] Merge SVE ternary FP operations This patch combines the four individual fused multiply-add optabs into one pattern and uses unspecs instead of rtx codes. This is part of a series of patches that change the SVE FP patterns so that they can describe cases in which the predicate isn't all-true. 2019-08-07 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md (fma4, *fma4) (fnma4, *fnma4, fnms4, *fnms4) (fms4, *fms4): Replace with... (4) (*4): ...these new patterns. Use unspecs instead of rtx codes. (cond_, *cond__2, *cond__4) (*cond__any): Add the predicate to SVE_COND_FP_TERNARY. From-SVN: r274189 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 91b314b11d2..85d0dfee0dd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2019-08-07 Richard Sandiford + + * config/aarch64/aarch64-sve.md (fma4, *fma4) + (fnma4, *fnma4, fnms4, *fnms4) + (fms4, *fms4): Replace with... + (4) + (*4): ...these new patterns. + Use unspecs instead of rtx codes. + (cond_, *cond__2, *cond__4) + (*cond__any): Add the predicate to SVE_COND_FP_TERNARY. + 2019-08-07 Richard Sandiford * config/aarch64/iterators.md (SVE_COND_FP_MAXMIN_PUBLIC): New diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index a9943295d18..37a611c0462 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -85,10 +85,6 @@ ;; ---- [INT] Dot product ;; ---- [INT] Sum of absolute differences ;; ---- [FP] General ternary arithmetic corresponding to unspecs -;; ---- [FP] FMLA and FMAD -;; ---- [FP] FMLS and FMSB -;; ---- [FP] FNMLA and FNMAD -;; ---- [FP] FNMLS and FNMSB ;; ;; == Comparisons and selects ;; ---- [INT,FP] Select based on predicates @@ -2469,13 +2465,46 @@ ;; - FNMSB ;; ------------------------------------------------------------------------- +;; Unpredicated floating-point ternary operations. +(define_expand "4" + [(set (match_operand:SVE_F 0 "register_operand") + (unspec:SVE_F + [(match_dup 4) + (match_operand:SVE_F 1 "register_operand") + (match_operand:SVE_F 2 "register_operand") + (match_operand:SVE_F 3 "register_operand")] + SVE_COND_FP_TERNARY))] + "TARGET_SVE" + { + operands[4] = aarch64_ptrue_reg (mode); + } +) + +;; Predicated floating-point ternary operations. +(define_insn "*4" + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") + (unspec:SVE_F + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (match_operand:SVE_F 2 "register_operand" "%w, 0, w") + (match_operand:SVE_F 3 "register_operand" "w, w, w") + (match_operand:SVE_F 4 "register_operand" "0, w, w")] + SVE_COND_FP_TERNARY))] + "TARGET_SVE" + "@ + \t%0., %1/m, %2., %3. + \t%0., %1/m, %3., %4. + movprfx\t%0, %4\;\t%0., %1/m, %2., %3." + [(set_attr "movprfx" "*,*,yes")] +) + ;; Predicated floating-point ternary operations with merging. (define_expand "cond_" [(set (match_operand:SVE_F 0 "register_operand") (unspec:SVE_F [(match_operand: 1 "register_operand") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand") (match_operand:SVE_F 3 "register_operand") (match_operand:SVE_F 4 "register_operand")] SVE_COND_FP_TERNARY) @@ -2496,7 +2525,8 @@ (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "0, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "0, w") (match_operand:SVE_F 3 "register_operand" "w, w") (match_operand:SVE_F 4 "register_operand" "w, w")] SVE_COND_FP_TERNARY) @@ -2516,7 +2546,8 @@ (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "w, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "w, w") (match_operand:SVE_F 3 "register_operand" "w, w") (match_operand:SVE_F 4 "register_operand" "0, w")] SVE_COND_FP_TERNARY) @@ -2536,7 +2567,8 @@ (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "w, w, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "w, w, w") (match_operand:SVE_F 3 "register_operand" "w, w, w") (match_operand:SVE_F 4 "register_operand" "w, w, w")] SVE_COND_FP_TERNARY) @@ -2561,174 +2593,6 @@ [(set_attr "movprfx" "yes")] ) -;; ------------------------------------------------------------------------- -;; ---- [FP] FMLA and FMAD -;; ------------------------------------------------------------------------- -;; Includes: -;; - FMAD -;; - FMLA -;; ------------------------------------------------------------------------- - -;; Unpredicated fma (%0 = (%1 * %2) + %3). -(define_expand "fma4" - [(set (match_operand:SVE_F 0 "register_operand") - (unspec:SVE_F - [(match_dup 4) - (fma:SVE_F (match_operand:SVE_F 1 "register_operand") - (match_operand:SVE_F 2 "register_operand") - (match_operand:SVE_F 3 "register_operand"))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - { - operands[4] = aarch64_ptrue_reg (mode); - } -) - -;; fma predicated with a PTRUE. -(define_insn "*fma4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (fma:SVE_F (match_operand:SVE_F 3 "register_operand" "%0, w, w") - (match_operand:SVE_F 4 "register_operand" "w, w, w") - (match_operand:SVE_F 2 "register_operand" "w, 0, w"))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - "@ - fmad\t%0., %1/m, %4., %2. - fmla\t%0., %1/m, %3., %4. - movprfx\t%0, %2\;fmla\t%0., %1/m, %3., %4." - [(set_attr "movprfx" "*,*,yes")] -) - -;; ------------------------------------------------------------------------- -;; ---- [FP] FMLS and FMSB -;; ------------------------------------------------------------------------- -;; Includes: -;; - FMLS -;; - FMSB -;; ------------------------------------------------------------------------- - -;; Unpredicated fnma (%0 = (-%1 * %2) + %3). -(define_expand "fnma4" - [(set (match_operand:SVE_F 0 "register_operand") - (unspec:SVE_F - [(match_dup 4) - (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 1 "register_operand")) - (match_operand:SVE_F 2 "register_operand") - (match_operand:SVE_F 3 "register_operand"))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - { - operands[4] = aarch64_ptrue_reg (mode); - } -) - -;; fnma predicated with a PTRUE. -(define_insn "*fnma4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 3 "register_operand" "%0, w, w")) - (match_operand:SVE_F 4 "register_operand" "w, w, w") - (match_operand:SVE_F 2 "register_operand" "w, 0, w"))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - "@ - fmsb\t%0., %1/m, %4., %2. - fmls\t%0., %1/m, %3., %4. - movprfx\t%0, %2\;fmls\t%0., %1/m, %3., %4." - [(set_attr "movprfx" "*,*,yes")] -) - -;; ------------------------------------------------------------------------- -;; ---- [FP] FNMLA and FNMAD -;; ------------------------------------------------------------------------- -;; Includes: -;; - FNMAD -;; - FNMLA -;; ------------------------------------------------------------------------- - -;; Unpredicated fnms (%0 = (-%1 * %2) - %3). -(define_expand "fnms4" - [(set (match_operand:SVE_F 0 "register_operand") - (unspec:SVE_F - [(match_dup 4) - (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 1 "register_operand")) - (match_operand:SVE_F 2 "register_operand") - (neg:SVE_F - (match_operand:SVE_F 3 "register_operand")))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - { - operands[4] = aarch64_ptrue_reg (mode); - } -) - -;; fnms predicated with a PTRUE. -(define_insn "*fnms4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 3 "register_operand" "%0, w, w")) - (match_operand:SVE_F 4 "register_operand" "w, w, w") - (neg:SVE_F - (match_operand:SVE_F 2 "register_operand" "w, 0, w")))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - "@ - fnmad\t%0., %1/m, %4., %2. - fnmla\t%0., %1/m, %3., %4. - movprfx\t%0, %2\;fnmla\t%0., %1/m, %3., %4." - [(set_attr "movprfx" "*,*,yes")] -) - -;; ------------------------------------------------------------------------- -;; ---- [FP] FNMLS and FNMSB -;; ------------------------------------------------------------------------- -;; Includes: -;; - FNMLS -;; - FNMSB -;; ------------------------------------------------------------------------- - -;; Unpredicated fms (%0 = (%1 * %2) - %3). -(define_expand "fms4" - [(set (match_operand:SVE_F 0 "register_operand") - (unspec:SVE_F - [(match_dup 4) - (fma:SVE_F (match_operand:SVE_F 1 "register_operand") - (match_operand:SVE_F 2 "register_operand") - (neg:SVE_F - (match_operand:SVE_F 3 "register_operand")))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - { - operands[4] = aarch64_ptrue_reg (mode); - } -) - -;; fms predicated with a PTRUE. -(define_insn "*fms4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (fma:SVE_F (match_operand:SVE_F 3 "register_operand" "%0, w, w") - (match_operand:SVE_F 4 "register_operand" "w, w, w") - (neg:SVE_F - (match_operand:SVE_F 2 "register_operand" "w, 0, w")))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - "@ - fnmsb\t%0., %1/m, %4., %2. - fnmls\t%0., %1/m, %3., %4. - movprfx\t%0, %2\;fnmls\t%0., %1/m, %3., %4." - [(set_attr "movprfx" "*,*,yes")] -) - ;; ========================================================================= ;; == Comparisons and selects ;; =========================================================================