From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 4 Oct 2020 13:10:06 +0000 (+0000)
Subject: use new extpower/intpower and pads.useCoreSize params
X-Git-Tag: partial-core-ls180-gdsii~43
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d96ff1334caa957e1becd2690b61a63f46a40b2;p=soclayout.git

use new extpower/intpower and pads.useCoreSize params
---

diff --git a/experiments9/coriolis2/ioring.py b/experiments9/coriolis2/ioring.py
index c61fa47..42ff14b 100644
--- a/experiments9/coriolis2/ioring.py
+++ b/experiments9/coriolis2/ioring.py
@@ -36,6 +36,9 @@ chip.update({ 'pads.ioPadGauge' : 'pxlib',
           #'chip.size'       : ( l(30200), l(30200) ),
           # no-core option (test_issuer but no actual core)
           'core.size'       : ( l(13000), l(13000) ),
-          'chip.size'       : ( l(17000), l(17000) ),
+          'chip.size'       : ( l(14400), l(14400) ),
+          'pads.useCoreSize': True,
+          'chip.n_extpower'  : 2,
+          'chip.n_intpower'  : 1,
           'chip.clockTree'  : True,
        })