From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Nov 2018 09:14:09 +0000 (+0000)
Subject: fix length=0 in fsw and fsd
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d984ad6b2c7a7917ad9eca4f0a31b9f7d9e359e;p=riscv-isa-sim.git

fix length=0 in fsw and fsd
---

diff --git a/id_regs.py b/id_regs.py
index 61fde4a..03e255d 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -103,10 +103,10 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
         elif "f128(" in f:
             src_flen = 128
             dest_flen = 128
-        elif "f64(" in f:
+        elif "f64(" in f or insn == 'fsd':
             src_flen = 64
             dest_flen = 64
-        elif "f32(" in f:
+        elif "f32(" in f or insn == 'fsw':
             src_flen = 32
             dest_flen = 32
         for pattern in patterns: