From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 Mar 2019 19:59:49 +0000 (+0000)
Subject: reduce args to FPNorm1Single
X-Git-Tag: ls180-24jan2020~1552
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0dabf8370f37c859ddeb49f9380d64139eb617bb;p=ieee754fpu.git

reduce args to FPNorm1Single
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 3b786699..06943719 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -1187,10 +1187,10 @@ class FPNorm1Single(FPState, FPID):
         self.out_z = FPNumBase(width, False)
         self.out_roundz = Signal(reset_less=True)
 
-    def setup(self, m, in_z, in_of, in_mid):
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.mod.setup(m, in_z, in_of, self.out_z)
+        self.mod.setup(m, i, self.out_z)
 
         if self.in_mid is not None:
             m.d.comb += self.in_mid.eq(in_mid)