From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 10 Nov 2020 16:21:51 +0000 (+0000)
Subject: add minerva nmigen-soc example
X-Git-Tag: convert-csv-opcode-to-binary~1846
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0dbab7b582bdcf7e75aadff81551abec621d81f2;p=libreriscv.git

add minerva nmigen-soc example
---

diff --git a/resources.mdwn b/resources.mdwn
index b54c1bf9c..4c514faf9 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -325,6 +325,8 @@ Some learning resources I found in the community:
   online.
 * [Minerva](https://github.com/lambdaconcept/minerva)
   An SOC written in Python nMigen DSL
+* Minerva example using nmigen-soc
+  <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>