From: lkcl Date: Tue, 13 Sep 2022 14:47:30 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~458 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0dd33a868bd5ec0b76ba68ac451f93e4eb03bb53;p=libreriscv.git --- diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index b1f672599..27e779cdd 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -44,8 +44,9 @@ It is also crucial to note that whilst this format augments instruction behaviour it works in conjunction with SVSTATE and other [[sv/sprs]]. All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB -and counting up as you move to the LSB end). All bit ranges are inclusive -(so `4:6` means bits 4, 5, and 6). +on the left +and counting up as you move rightwards to the LSB end). All bit ranges are inclusive +(so `4:6` means bits 4, 5, and 6, in MSB0 order). 64-bit instructions are split into two 32-bit words, the prefix and the suffix. The prefix always comes before the suffix in PC order.