From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 25 Jan 2019 18:25:25 +0000 (+0100)
Subject: Fixed Anlogic simulation model
X-Git-Tag: yosys-0.9~319^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0de328da8ffea4902c52b286d7b38d67a714c742;p=yosys.git

Fixed Anlogic simulation model
---

diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v
index 60a367928..058e76605 100644
--- a/techlibs/anlogic/cells_sim.v
+++ b/techlibs/anlogic/cells_sim.v
@@ -17,7 +17,7 @@ module AL_MAP_LUT1 (
 );
 	parameter [1:0] INIT = 2'h0;
 	parameter EQN = "(A)";
-	assign Y = INIT >> A;
+	assign o = INIT >> a;
 endmodule
 
 module AL_MAP_LUT2 (