From: Tom Stellard <thomas.stellard@amd.com>
Date: Wed, 5 Sep 2012 18:35:21 +0000 (-0400)
Subject: radeon/llvm: Add register encoding for VCC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0df2753ad21175d8914a8c2ca512cf79246c10fd;p=mesa.git

radeon/llvm: Add register encoding for VCC

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
---

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
index 438d2acf989..ca4b579dcce 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -280,6 +280,7 @@ unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
 
 unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
   switch (reg) {
+    case AMDGPU::VCC: return 106;
     case AMDGPU::M0: return 124;
     case AMDGPU::EXEC: return 126;
     case AMDGPU::EXEC_LO: return 126;