From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 17:44:10 +0000 (+0200)
Subject: Add support for zero-width signals to Verilog back-end, fixes #948
X-Git-Tag: yosys-0.9~175^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e0c80fac883a6f512a94aecdc3c915b8cacb562;p=yosys.git

Add support for zero-width signals to Verilog back-end, fixes #948

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 855409d0b..9967482d6 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -187,6 +187,10 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 {
 	if (width < 0)
 		width = data.bits.size() - offset;
+	if (width == 0) {
+		f << "\"\"";
+		return;
+	}
 	if (nostr)
 		goto dump_hex;
 	if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
@@ -340,6 +344,10 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
 
 void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 {
+	if (GetSize(sig) == 0) {
+		f << "\"\"";
+		return;
+	}
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk());
 	} else {