From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 09:20:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~542
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e1ea0f4dcfdd9312c5f6e56d997a8be6b61b569;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 38dcd0a9e..301ee34d7 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -99,3 +99,18 @@ Note that, interestingly, due to the useful side-effects of `VLSET` mode
 and `svstep` mode it is actually useful to use Branch Conditional even
 to perform no actual branch operation, i.e to point to the instruction
 after the branch.
+
+Available options to combine:
+
+* `BO` to select whether the CR bit being tested is zero or nonzero
+* `R30` and `~R30` and other predicate mask options including CR and
+  inverted CR bit testing
+* `sz` and `SNZ` to insert either zeros or ones in place of masked-out
+  predicate bits
+* `ALL` or `ANY` behaviour corresponding to `AND` of all tests and
+  `OR` of all tests, respectively.
+
+Pseudocode for Horizontal-First Mode:
+
+```
+```