From: lkcl <lkcl@web>
Date: Sun, 3 Jul 2022 12:07:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1389
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e282e512367176561482ec04c9ef7c7d381840e;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index c3c2100ca..4f7eb8c8b 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -104,22 +104,25 @@ Pages being developed and examples
   or are not immediately apparent despite the RISC paradigm
 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
 * [[sv/sprs]] SPRs
-* SVP64 "Modes":
-  - For condition register operations see [[sv/cr_ops]] - SVP64 Condition
+
+SVP64 "Modes":
+
+* For condition register operations see [[sv/cr_ops]] - SVP64 Condition
     Register ops: Guidelines
     on Vectorisation of any v3.0B base operations which return
     or modify a Condition Register bit or field.
-  - For LD/ST Modes, see [[sv/ldst]].
-  - For Branch modes, see [[sv/branches]] - SVP64 Conditional Branch
+* For LD/ST Modes, see [[sv/ldst]].
+* For Branch modes, see [[sv/branches]] - SVP64 Conditional Branch
     behaviour: All/Some Vector CRs
-  - For arithmetic and logical, see [[sv/normal]]
-  - [[sv/mv.vec]] pack/unpack move to and from vec2/3/4,
+* For arithmetic and logical, see [[sv/normal]]
+* [[sv/mv.vec]] pack/unpack move to and from vec2/3/4,
     actually an RM.EXTRA Mode and a [[sv/remap]] mode
 
 Core SVP64 instructions:
 
 * [[sv/setvl]] the Cray-style "Vector Length" instruction
-* [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
+* [[sv/remap]] "Remapping" for Matrix Multiply, DCT/FFT
+  and RGB-style "Structure Packing"
   as well as Indexing. Describes svindex, svremap and svshape and
   associated SPRs.
 * [[sv/svstep]] Key stepping instruction, primarily for
@@ -150,15 +153,16 @@ necessary but performance and power consumption may be (or, is already)
 compromised
 in certain workloads and use-cases without them.
 
-Vector-related:
+Vector-related but still Scalar:
 
 * [[sv/mv.swizzle]] vec2/3/4 Swizzles (RGBA, XYZW) for 3D and CUDA.
   designed as a Scalar instruction.
 * [[sv/vector_ops]] scalar operations needed for supporting vectors
+* [[sv/cr_int_predication]] scalar instructions needed for
+  effective predication
 
-Scalar Instructions:
+Stand-alone Scalar Instructions:
 
-* [[sv/cr_int_predication]] instructions needed for effective predication
 * [[sv/bitmanip]]
 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
 * [[sv/fclass]] detect class of FP numbers
@@ -175,6 +179,9 @@ Scalar Instructions:
 
 # Other Scalable Vector ISAs
 
+These Scalable Vector ISAs are listed to aid in understanding and
+context of what is involved.
+
 * Original Cray ISA
   <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
 * NEC SX Aurora (still in production, inspired by Cray)
@@ -188,7 +195,7 @@ Scalar Instructions:
 
 A comprehensive list of 3D GPU, Packed SIMD, Predicated-SIMD and true Scalable
 Vector ISAs may be found at the [[sv/vector_isa_comparison]] page.
-Note: AVX-512 and SVE2 are *not strict Vector ISAs*, they are Predicated-SIMD.
+Note: AVX-512 and SVE2 are *not Vector ISAs*, they are Predicated-SIMD.
 *Public discussions have taken place at Conferences attended by both Intel
 and ARM on adding a `setvl` instruction which would easily make both
 AVX-512 and SVE2 truly "Scalable".*