From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 17 Dec 2011 14:00:18 +0000 (+0100)
Subject: Multiply system clock
X-Git-Tag: 24jan2021_ls180~3281
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e30d67fa3af6882f0426e70a8e74f2d46b21ed5;p=litex.git

Multiply system clock
---

diff --git a/constraints.py b/constraints.py
index 8ffd501d..f37b6b27 100644
--- a/constraints.py
+++ b/constraints.py
@@ -1,4 +1,4 @@
-def get(ns, reset0, norflash0, uart0):
+def get(ns, clkfx_sys, reset0, norflash0, uart0):
 	constraints = []
 	def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
 		constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
@@ -8,6 +8,8 @@ def get(ns, reset0, norflash0, uart0):
 			add(signal, p, i, iostandard, extra)
 			i += 1
 	
+	add(clkfx_sys.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
+	
 	add(reset0.trigger_reset, "AA4")
 	add(reset0.ac97_rst_n, "D6")
 	add(reset0.videoin_rst_n, "W17")
@@ -39,8 +41,6 @@ def get(ns, reset0, norflash0, uart0):
 		r += ";\n"
 	
 	r += """
-NET "sys_clk" LOC = AB11 | IOSTANDARD = LVCMOS33;
-NET "sys_clk" TNM_NET = "GRPclk50";
 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
 	"""
 	
diff --git a/top.py b/top.py
index 75e8f70d..d4ea784f 100644
--- a/top.py
+++ b/top.py
@@ -2,10 +2,14 @@ from migen.fhdl.structure import *
 from migen.fhdl import convtools, verilog, autofragment
 from migen.bus import wishbone, csr, wishbone2csr
 
-from milkymist import m1reset, lm32, norflash, uart
+from milkymist import m1reset, clkfx, lm32, norflash, uart
 import constraints
 
 def get():
+	MHz = 1000000
+	clk_freq = 80*MHz
+	
+	clkfx_sys = clkfx.Inst(50*MHz, clk_freq)
 	reset0 = m1reset.Inst()
 	
 	cpu0 = lm32.Inst()
@@ -16,13 +20,16 @@ def get():
 		[(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
 		register=True,
 		offset=1)
-	uart0 = uart.Inst(0, 50*1000*1000, baud=115200)
+	uart0 = uart.Inst(0, clk_freq, baud=115200)
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
 	
-	frag = autofragment.from_local() + Fragment(pads={reset0.trigger_reset})
+	frag = autofragment.from_local()
 	vns = convtools.Namespace()
-	src_verilog = verilog.Convert(frag, name="soc",
+	src_verilog = verilog.Convert(frag,
+		{clkfx_sys.clkin, reset0.trigger_reset},
+		name="soc",
+		clk_signal=clkfx_sys.clkout,
 		rst_signal=reset0.sys_rst,
 		ns=vns)
-	src_ucf = constraints.get(vns, reset0, norflash0, uart0)
+	src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
 	return (src_verilog, src_ucf)