From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 12 May 2019 16:37:25 +0000 (+0100)
Subject: experimenting / debugging score6600
X-Git-Tag: div_pipeline~2065
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e387cdcfb365c988cd2b04da6ef05346f1635c1;p=soc.git

experimenting / debugging score6600
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 27672774..3b2f2009 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -417,8 +417,8 @@ def scoreboard_sim(dut, alusim):
     yield dut.int_store_i.eq(0)
 
     for i in range(1, dut.n_regs):
-        yield dut.intregs.regs[i].reg.eq(i)
-        alusim.setval(i, i)
+        yield dut.intregs.regs[i].reg.eq(i*2)
+        alusim.setval(i, i*2)
 
     yield
     yield
@@ -452,8 +452,8 @@ def scoreboard_sim(dut, alusim):
             break
             if dest not in [src1, src2]:
                 break
-        src1 = 7
-        src2 = 1
+        src1 = 1
+        src2 = 4
         dest = 1
 
         op = randint(0, 1)