From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Jul 2019 12:03:46 +0000 (+0100)
Subject: add comments
X-Git-Tag: ls180-24jan2020~825
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e3d645f096cd59501e0bb4ffdc01a57cac30503;p=ieee754fpu.git

add comments
---

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 9c51c3ca..5d622132 100644
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -30,6 +30,12 @@ normpack  - FPNormToPack           ispec FPAddStage1Data
                             CorrectionsMod,
                             PackMod
 
+This pipeline has a 3 clock latency, and, with the separation into
+separate "modules", it is quite clear how to create longer-latency
+pipelines (if needed) - just create a new, longer top-level (FPADDBasePipe
+alternative) and construct shorter pipe stages using the building blocks,
+RoundMod, FPAddStage0Mod etc.
+
 """
 
 from nmigen import Module