From: lkcl <lkcl@web>
Date: Sun, 19 Jun 2022 19:54:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e4d9a9cc7d35d1d2ac129162c04aa6ff9e1ae95;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index e7fe1218a..ede107e25 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -468,6 +468,18 @@ augmented to 7 bits in length.
 
 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
 
+## MVRM-2P-1S1D
+
+| Field Name | Field bits | Description                     |
+|------------|------------|----------------------------|
+| Rdest_EXTRA2 | `10:11`  | extends Rdest (R\*\_EXTRA2 Encoding)   |
+| Rsrc_EXTRA2  | `12:13`  | extends Rsrc  (R\*\_EXTRA2 Encoding)   |
+| PACK_en      | `14`     | Enable pack              |
+| UNPACK_en    | `15`     | Enable unpack             |
+| MASK_SRC     | `16:18`  | Execution Mask for Source     |
+
+for [[sv/mv.vec]], [[sv/mv.swizzle]] and also LD/ST (without index)
+
 ## RM-1P-2S1D
 
 single-predicate, three registers (2 read, 1 write)