From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 17:45:39 +0000 (-0700)
Subject: Move 'shregmap -tech xilinx' into map_cells
X-Git-Tag: yosys-0.9~171^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e76718720895a4985a7fad24052a61550acdeda;p=yosys.git

Move 'shregmap -tech xilinx' into map_cells
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 1449e792f..d6e7c2623 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -112,14 +112,14 @@ struct SynthXilinxPass : public Pass
 		log("        memory_map\n");
 		log("        dffsr2dff\n");
 		log("        dff2dffe\n");
-		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
-		log("        pmux2shiftx (without '-nosrl' only)\n");
-		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
-		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
 		log("        techmap -map +/xilinx/arith_map.v\n");
 		log("        opt -fast\n");
 		log("\n");
 		log("    map_cells:\n");
+		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
+		log("        pmux2shiftx (without '-nosrl' only)\n");
+		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
+		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
 		log("        techmap -map +/xilinx/cells_map.v\n");
 		log("        clean\n");
 		log("\n");
@@ -269,6 +269,18 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
 
+			if (vpr) {
+				Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+			} else {
+				Pass::call(design, "techmap -map +/xilinx/arith_map.v");
+			}
+
+			Pass::call(design, "hierarchy -check");
+			Pass::call(design, "opt -fast");
+		}
+
+		if (check_label(active, run_from, run_to, "map_cells"))
+		{
 			if (!nosrl) {
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
@@ -278,23 +290,12 @@ struct SynthXilinxPass : public Pass
 				//   so attempt to convert $pmux-es to the former
 				Pass::call(design, "pmux2shiftx");
 				// pmux2shiftx can leave behind a $pmux with a single entry
-				//   -- need this to clean that up
+				//   -- need this to clean that up before shregmap
 				Pass::call(design, "opt_expr -mux_undef");
+				// shregmap with '-tech xilinx' infers variable length shift regs
 				Pass::call(design, "shregmap -tech xilinx -minlen 3");
 			}
 
-			if (vpr) {
-				Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
-			} else {
-				Pass::call(design, "techmap -map +/xilinx/arith_map.v");
-			}
-
-			Pass::call(design, "hierarchy -check");
-			Pass::call(design, "opt -fast");
-		}
-
-		if (check_label(active, run_from, run_to, "map_cells"))
-		{
 			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 			Pass::call(design, "clean");
 		}
@@ -305,6 +306,8 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
 			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
+			// This shregmap call infers fixed length shift registers after abc
+			//   has performed any necessary retiming
 			if (!nosrl)
 				Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");