From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 07:11:13 +0000 (+0200)
Subject: Merge pull request #941 from Wren6991/sim_lib_io_clke
X-Git-Tag: yosys-0.9~180
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e7901e45cc54a9bf76a86dd58092f310f72c90a;p=yosys.git

Merge pull request #941 from Wren6991/sim_lib_io_clke

ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
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0e7901e45cc54a9bf76a86dd58092f310f72c90a