From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Oct 2018 01:04:57 +0000 (+0100)
Subject: identify type of instruction with additional #defines
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e8049d8d01af4d071ee689dd7fe01b2ae516ec8;p=riscv-isa-sim.git

identify type of instruction with additional #defines
---

diff --git a/id_regs.py b/id_regs.py
index 0d732b3..1812e4a 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -107,4 +107,29 @@ if __name__ == '__main__':
         with open(regsname, "w") as f:
             txt = find_registers(fname)
             txt += "\n#define INSN_%s\n" % insn.upper()
+            # help identify type of register
+            if insn in ['beq', 'bne', 'blt', 'bltu', 'bge', 'bgeu']:
+                txt += "#define INSN_TYPE_BRANCH\n"
+            elif insn in ['c_ld', 'c_bnez']:
+                txt += "\n#define INSN_TYPE_C_BRANCH\n"
+            elif insn in ['c_lwsp', 'c_ldsp', 'c_lqsp', 'c_flwsp', 'c_fldsp']:
+                txt += "\n#define INSN_TYPE_C_STACK_LD\n"
+            elif insn in ['c_swsp', 'c_sdsp', 'c_sqsp', 'c_fswsp', 'c_fsdsp']:
+                txt += "\n#define INSN_TYPE_C_STACK_ST\n"
+            elif insn in ['c_lw', 'c_ld', 'c_lq', 'c_flw', 'c_fld']:
+                txt += "\n#define INSN_TYPE_C_LD\n"
+            elif insn in ['c_sw', 'c_sd', 'c_sq', 'c_fsw', 'c_fsd']:
+                txt += "\n#define INSN_TYPE_C_ST\n"
+            elif insn in ['c_beqz', 'c_bnez']:
+                txt += "\n#define INSN_TYPE_C_BRANCH\n"
+            elif insn.startswith("c_"):
+                txt += "#define INSN_TYPE_C\n"
+            elif insn.startswith("fmv") or \
+                 insn.startswith("fcvt") or \
+                 insn.startswith("fsgn"):
+                txt += "#define INSN_TYPE_FP_DUALOP\n"
+            elif insn.startswith("feq") or \
+                 insn.startswith("flt") or \
+                 insn.startswith("fle"):
+                txt += "#define INSN_TYPE_FP_BRANCH\n"
             f.write(txt)