From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 May 2021 13:53:17 +0000 (+0000)
Subject: add TODO into tsmc_c018 coriolis2 settings.py
X-Git-Tag: LS180_RC3~38
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e83dd816fda283f4b2cc1533253891310552789;p=soclayout.git

add TODO into tsmc_c018 coriolis2 settings.py
---

diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py
index 70993c7..2a72d23 100644
--- a/experiments9/tsmc_c018/coriolis2/settings.py
+++ b/experiments9/tsmc_c018/coriolis2/settings.py
@@ -32,6 +32,33 @@ LibreSOCIO.setup()
 LibreSOCMem.setup()
 pll.setup()
 
+# XXX TODO, important! fix the directions of the PLL cells
+# https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/47
+def fix_pll():
+    for cell in pll.getCells():
+        for net in cell.getNets():
+            # TODO: review
+            if net.getName() == 'vdd':
+                net.setType( Net.Type.POWER )
+                net.setDirection( Net.Direction.IN )
+            # TODO: review
+            elif net.getName() == 'vss':
+                net.setType( Net.Type.GROUND )
+                net.setDirection( Net.Direction.IN )
+            # TODO: review
+            elif net.getName() == 'ck':
+                net.setType( Net.Type.CLOCK )
+                net.setDirection( Net.Direction.IN )
+            # TODO review, should be good
+            elif net.getName() in ['div_out_test', 'vco_test_ana', 'out_v']:
+                net.setDirection( Net.Direction.OUT )
+            # last option, set it as an input
+            else:
+                net.setDirection( Net.Direction.IN )
+
+# XXX TODO uncomment this line: fix_pll()
+
+# XXX TODO same thing for spblock_512xxxetcxxx for "q" output data
 
 db = DataBase.getDB()
 af = AllianceFramework.get()