From: Tobias Platen Date: Thu, 9 Apr 2020 09:12:34 +0000 (+0200) Subject: fix 'Object is not an nMigen signal' error in test_sim.py X-Git-Tag: div_pipeline~1435^2~31 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e86cfa84513b07ea3f485071d1c9b9e5779eacd;p=soc.git fix 'Object is not an nMigen signal' error in test_sim.py --- diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index 1c31075a..068beacd 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -46,7 +46,7 @@ class DecoderTestCase(FHDLTestCase): sim.add_process(process) with sim.write_vcd("simulator.vcd", "simulator.gtkw", - traces=[pdecode2.ports()]): + traces=pdecode2.ports()): sim.run() def test_example(self):