From: Segher Boessenkool Date: Tue, 4 Jun 2019 23:36:49 +0000 (+0200) Subject: rs6000: Add p9kf and p9tf isa values X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e9449e69f797c4274f3463e1e10a1796a455e42;p=gcc.git rs6000: Add p9kf and p9tf isa values This adds "p9kf" and "p9tf" isa values, to be used for instruction alternatives where KFmode resp. TFmode is used. * config/rs6000/rs6000.md (define_attr "isa"): Add p9kf and p9tf. (define_attr "enabled"): Handle those new isa values. From-SVN: r271938 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 857b30710ff..453f017c1a5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-06-04 Segher Boessenkool + + * config/rs6000/rs6000.md (define_attr "isa"): Add p9kf and p9tf. + (define_attr "enabled"): Handle those new isa values. + 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md (define_mode_attr VSr4): Delete. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b8b246a5a2d..b1f3bc3aac0 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -267,7 +267,7 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v" (const_string "any")) +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? (define_attr "enabled" "" @@ -298,6 +298,14 @@ (and (eq_attr "isa" "p9v") (match_test "TARGET_P9_VECTOR")) (const_int 1) + + (and (eq_attr "isa" "p9kf") + (match_test "TARGET_FLOAT128_TYPE")) + (const_int 1) + + (and (eq_attr "isa" "p9tf") + (match_test "FLOAT128_VECTOR_P (TFmode)")) + (const_int 1) ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor