From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Apr 2018 23:41:58 +0000 (+0100)
Subject: add load/store pseudocode
X-Git-Tag: convert-csv-opcode-to-binary~5687
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0e9a2dcc9be89b0a67fc5559a3fd6ea6af9e0966;p=libreriscv.git

add load/store pseudocode
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index c0a8f8b24..00275e2ef 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -604,10 +604,42 @@ Lots to be discussed.
 
 ## 17.18 Vector Load/Store Instructions
 
-These may not have a direct equivalent in Simple-V, except if mask/tagging
-is to be deployed.
+The Vector Load/Store instructions as proposed in V are extremely powerful
+and can be used for reordering and regular restructuring.
 
-To be discussed.
+Vector Load:
+
+    if (unit-strided) stride = elsize;
+    else stride = areg[as2]; // constant-strided
+    for (int i=0; i<vl; ++i)
+      if ([!]preg[p][i])
+        for (int j=0; j<seglen+1; j++)
+          vreg[vd+j][i] = mem[areg[as1] + (i*(seglen+1)+j)*stride];
+
+Store:
+
+    if (unit-strided) stride = elsize;
+    else stride = areg[as2]; // constant-strided
+    for (int i=0; i<vl; ++i)
+      if ([!]preg[p][i])
+        for (int j=0; j<seglen+1; j++)
+          mem[areg[base] + (i*(seglen+1)+j)*stride] = vreg[vd+j][i];
+
+Indexed Load:
+
+    for (int i=0; i<vl; ++i)
+      if ([!]preg[p][i])
+        for (int j=0; j<seglen+1; j++)
+          vreg[vd+j][i] = mem[sreg[base] + vreg[vs2][i] + j*elsize];
+
+Indexed Store:
+
+    for (int i=0; i<vl; ++i)
+    if ([!]preg[p][i])
+      for (int j=0; j<seglen+1; j++)
+        mem[sreg[base] + vreg[vs2][i] + j*elsize] = vreg[vd+j][i];
+
+Keeping these instructions as-is for Simple-V is highly recommended.
 
 ## 17.19 Vector Register Gather