From: lkcl <lkcl@web>
Date: Tue, 20 Sep 2022 12:28:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~351
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ea69dd74d05923852819433f05fae7a550b22df;p=libreriscv.git

---

diff --git a/openpower/sv/vector_isa_comparison.mdwn b/openpower/sv/vector_isa_comparison.mdwn
index 005edc8b3..b8c51490c 100644
--- a/openpower/sv/vector_isa_comparison.mdwn
+++ b/openpower/sv/vector_isa_comparison.mdwn
@@ -77,7 +77,9 @@ SIMD ISAs used features "inspired" from Scalable Vector ISAs.
 * ARM NEON - accurately described as a Packed SIMD ISA in
   all literature.
 * ARM SVE / SVE2 - **not a Scalable Vector ISA**, it is actually
-  a hybrid PackedSIMD/PredicatedSIMD ISA.
+  a hybrid PackedSIMD/PredicatedSIMD ISA: with 4-operand instructions
+  being overwrite to fit into 32-bit there was no room for a predicate
+  mask.
   The "Scaling" is, rather unfortunately, a parameter
   that is chosen by the *Hardware Architect*, rather than
   the programmer. The actual "Scalar" part as far as the programmer
@@ -90,6 +92,14 @@ SIMD ISAs used features "inspired" from Scalable Vector ISAs.
   going directly against the advice given on ARM's developer
   documentation.
 
+A good analogy explaining why "Silicon-Partner Scalability" is
+catastrophic is to note that the situation is near-identical to when IBM
+extended Power ISA from 32 to 64-bit.  Existing 32-bit systems
+were **unable** to run or trap-and-emulate 64-bit instructions
+**because they were the exact same opcodes** and the "Silicon Scalability"
+of both RVV and ARM SVE/2 is the exact same mistake, but much
+worse.  At least IBM provided an `MSR.SF` bit.
+
 The saving grace of PackedSIMD VSX is that it did not fall to the
 seduction outlined in the "SIMD Considered Harmful" article
 <https://www.sigarch.org/simd-instructions-considered-harmful/>.
@@ -99,7 +109,7 @@ resulted in ISA poisoning such as that suffered by x86 (AVX).
 
 # Actual 3D GPU Architectures and ISAs (all SIMD)
 
-All of these are not Vector ISAs, they are SIMD ISAs.
+All of these are not Scalable Vector ISAs, they are SIMD ISAs.
 
 * Broadcom Videocore
   <https://github.com/hermanhermitage/videocoreiv>
@@ -127,9 +137,11 @@ All of these are not Vector ISAs, they are SIMD ISAs.
 * MRISC32 ISA Manual (under active development)
   <https://github.com/mrisc32/mrisc32/tree/master/isa-manual>
 * Mitch Alsup's MyISA 66000 Vector Processor ISA Manual is available from
-  Mitch on direct contact with him.  It is a different approach from the
+  Mitch under NDA
+  on direct contact with him.  It is a different approach from the
   others, which may be termed "Cray-Style Horizontal-First" Vectorisation.
-  66000 is a *Vertical-First* Vector ISA.
+  66000 is a *Vertical-First* Vector ISA with hardware-level
+  auto-vectorisation.
 * [ETA-10](http://50.204.185.175/collections/catalog/102641713)
   an extremely rare Scalable Vector Architecture from 1986,
   similar to the CDC Cyber 205.