From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Mar 2019 20:08:43 +0000 (-0700)
Subject: Make output port a non chain user
X-Git-Tag: yosys-0.9~171^2~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ea7eba5f13b20de28181a66181ee821820027db;p=yosys.git

Make output port a non chain user
---

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index d95cadde5..3b3170e04 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -118,7 +118,7 @@ struct ShregmapTechXilinx7 : ShregmapTech
 		auto it = sigbit_to_shiftx_offset.find(bit);
 		if (it == sigbit_to_shiftx_offset.end())
 			return;
-		if (cell->type == "$shiftx" && port == "\\A")
+		if (cell && cell->type == "$shiftx" && port == "\\A")
 			return;
 		sigbit_to_shiftx_offset.erase(it);
 	}
@@ -228,8 +228,10 @@ struct ShregmapWorker
 	for (auto wire : module->wires())
 	{
 	    if (wire->port_output || wire->get_bool_attribute("\\keep")) {
-		for (auto bit : sigmap(wire))
+		for (auto bit : sigmap(wire)) {
 		    sigbit_with_non_chain_users.insert(bit);
+		    if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
+		}
 	    }
 
 	    if (wire->attributes.count("\\init")) {