From: Andreas Hansson <andreas.hansson@arm.com>
Date: Tue, 5 May 2015 07:22:24 +0000 (-0400)
Subject: mem: Add missing stats update for uncacheable MSHRs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ebbf3f9512609c089257158abd14b9366b72b52;p=gem5.git

mem: Add missing stats update for uncacheable MSHRs

This patch adds a missing counter update for the uncacheable
accesses. By updating this counter we also get a meaningful average
latency for uncacheable accesses (previously inf).
---

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a530001ae..6817db41e 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -701,8 +701,10 @@ Cache::recvTimingReq(PacketPtr pkt)
             }
         } else {
             // no MSHR
-            if (!pkt->req->isUncacheable()) {
-                assert(pkt->req->masterId() < system->maxMasters());
+            assert(pkt->req->masterId() < system->maxMasters());
+            if (pkt->req->isUncacheable()) {
+                mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
+            } else {
                 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
             }