From: Wesley W. Terpstra <wesley@sifive.com>
Date: Sat, 13 May 2017 05:59:48 +0000 (-0700)
Subject: xilinxvc707pciex1: push to a dedicated clock domain
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ed21ba46590a23434d7ee55fa47bda3e114b4cd;p=sifive-blocks.git

xilinxvc707pciex1: push to a dedicated clock domain
---

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index ae7cca5..9bb0c05 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -20,9 +20,9 @@ class XilinxVC707PCIeX1IO extends Bundle with VC707AXIToPCIeX1IOSerial
 }
 
 class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
-  val slave = TLInputNode()
-  val control = TLInputNode()
-  val master = TLOutputNode()
+  val slave = TLAsyncInputNode()
+  val control = TLAsyncInputNode()
+  val master = TLAsyncOutputNode()
   val intnode = IntOutputNode()
 
   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
@@ -33,21 +33,24 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
     AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
     AXI4IdIndexer(idBits=4)(
     TLToAXI4(beatBytes=8)(
-    slave)))))
+    TLAsyncCrossingSink()(
+    slave))))))
 
   axi_to_pcie_x1.control :=
     AXI4Buffer()(
     AXI4UserYanker()(
     TLToAXI4(beatBytes=4)(
     TLFragmenter(4, p(coreplex.CacheBlockBytes))(
-    control))))
+    TLAsyncCrossingSink()(
+    control)))))
 
   master :=
+    TLAsyncCrossingSource()(
     TLWidthWidget(8)(
     AXI4ToTL()(
     AXI4UserYanker(capMaxFlight=Some(8))(
     AXI4Fragmenter()(
-    axi_to_pcie_x1.master))))
+    axi_to_pcie_x1.master)))))
 
   intnode := axi_to_pcie_x1.intnode
 
diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index d64d19a..c994856 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -8,15 +8,18 @@ import rocketchip.{
   HasTopLevelNetworksModule,
   HasTopLevelNetworksBundle
 }
-import uncore.tilelink2.TLWidthWidget
+import uncore.tilelink2._
 
 trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
 
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-  fsb.node := xilinxvc707pcie.master
-  xilinxvc707pcie.slave   := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  intBus.intnode := xilinxvc707pcie.intnode
+  private val intXing = LazyModule(new IntXing)
+
+  fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
+  xilinxvc707pcie.slave   := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+  xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+  intBus.intnode := intXing.intnode
+  intXing.intnode := xilinxvc707pcie.intnode
 }
 
 trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
@@ -28,4 +31,7 @@ trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
   val io: HasPeripheryXilinxVC707PCIeX1Bundle
 
   io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+
+  outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
+  outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
 }