From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Sep 2018 01:17:49 +0000 (+0100)
Subject: clarify sv cam table
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0edd880c3fe71d60b144b822b94a116ec9c408b5;p=riscv-isa-sim.git

clarify sv cam table
---

diff --git a/riscv/sv.h b/riscv/sv.h
index ba40926..58e5724 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -5,6 +5,8 @@
 
 // this table is for the CSRs (4? for RV32E, 16 for other types)
 // it's a CAM that's used to generate 2 tables (below)
+// just as in RV, writing to entries in this CAM *clears*
+// all entries with a higher index
 typedef struct {
     unsigned int type   : 1; // 0=INT, 1=FP
     unsigned int regkey : 5; // 5 bits