From: james <james@web>
Date: Thu, 23 Nov 2023 13:05:38 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ee34e886234695e2adcdc8e0e307a3d14b0a76a;p=libreriscv.git

---

diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index 7a60e21c9..45838dd8c 100644
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -62,7 +62,7 @@ Key phases of this project are:
 
 * Implementation of Simple-V in the Libre-SOC Simulator, ISACaller.
 
-* Assembler and disassembler of RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
+* Definition of assembler and disassembler for RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
 
 * Upgrading (with the newly created instructions and forms) sv-spike assembler development which was prototyped previously for Simple-V Specification:
   <https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>