From: whitequark <whitequark@whitequark.org>
Date: Fri, 14 Dec 2018 16:39:52 +0000 (+0000)
Subject: compat.sim: match clock period.
X-Git-Tag: working~249
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ef5ced49224252fabc0be083a28840b69096bf2;p=nmigen.git

compat.sim: match clock period.
---

diff --git a/nmigen/compat/sim/__init__.py b/nmigen/compat/sim/__init__.py
index c2a7c7b..4ee0454 100644
--- a/nmigen/compat/sim/__init__.py
+++ b/nmigen/compat/sim/__init__.py
@@ -18,7 +18,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name
 
     with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
         for domain, period in clocks.items():
-            sim.add_clock(period, domain)
+            sim.add_clock(period / 1e9, domain)
         for domain, process in generators.items():
             sim.add_sync_process(process, domain)
         sim.run()