From: Kyrylo Tkachov Date: Tue, 4 Aug 2015 10:41:31 +0000 (+0000) Subject: [AArch64][12/14] Target attributes and target pragmas tests X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0efacb57a40412c029d4b33503f2bad15538072c;p=gcc.git [AArch64][12/14] Target attributes and target pragmas tests * gcc.target/aarch64/pragma_cpp_predefs_1.c: New test. * gcc.target/aarch64/target_attr_1.c: Likewise. * gcc.target/aarch64/target_attr_2.c: Likewise. * gcc.target/aarch64/target_attr_3.c: Likewise. * gcc.target/aarch64/target_attr_4.c: Likewise. * gcc.target/aarch64/target_attr_5.c: Likewise. * gcc.target/aarch64/target_attr_6.c: Likewise. * gcc.target/aarch64/target_attr_7.c: Likewise. * gcc.target/aarch64/target_attr_8.c: Likewise. * gcc.target/aarch64/target_attr_9.c: Likewise. * gcc.target/aarch64/target_attr_10.c: Likewise. * gcc.target/aarch64/target_attr_11.c: Likewise. * gcc.target/aarch64/target_attr_12.c: Likewise. * gcc.target/aarch64/target_attr_13.c: Likewise. * gcc.target/aarch64/target_attr_14.c: Likewise. * gcc.target/aarch64/target_attr_15.c: Likewise. From-SVN: r226565 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 244ed9602b7..37b41687aba 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,22 @@ +2015-08-04 Kyrylo Tkachov + + * gcc.target/aarch64/pragma_cpp_predefs_1.c: New test. + * gcc.target/aarch64/target_attr_1.c: Likewise. + * gcc.target/aarch64/target_attr_2.c: Likewise. + * gcc.target/aarch64/target_attr_3.c: Likewise. + * gcc.target/aarch64/target_attr_4.c: Likewise. + * gcc.target/aarch64/target_attr_5.c: Likewise. + * gcc.target/aarch64/target_attr_6.c: Likewise. + * gcc.target/aarch64/target_attr_7.c: Likewise. + * gcc.target/aarch64/target_attr_8.c: Likewise. + * gcc.target/aarch64/target_attr_9.c: Likewise. + * gcc.target/aarch64/target_attr_10.c: Likewise. + * gcc.target/aarch64/target_attr_11.c: Likewise. + * gcc.target/aarch64/target_attr_12.c: Likewise. + * gcc.target/aarch64/target_attr_13.c: Likewise. + * gcc.target/aarch64/target_attr_14.c: Likewise. + * gcc.target/aarch64/target_attr_15.c: Likewise. + 2015-08-04 Kyrylo Tkachov * gcc.target/aarch64/target_attr_crypto_ice_1.c: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_1.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_1.c new file mode 100644 index 00000000000..bfb044f5d14 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_1.c @@ -0,0 +1,255 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8-a+crypto" } */ + +/* Test that pragma option pushing and popping works. + Also that CPP predefines redefinitions on #pragma works. */ + +#pragma GCC push_options +#pragma GCC target ("arch=armv8-a+nofp+nosimd") +#ifdef __ARM_FEATURE_FMA +#error "__ARM_FEATURE_FMA is defined but should not be!" +#endif + +#ifdef __ARM_FP +#error "__ARM_FP is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("arch=armv8-a+fp+nosimd") +#ifndef __ARM_FP +#error "__ARM_FP is not defined but should be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("arch=armv8-a+fp+simd") + +#ifndef __ARM_NEON +#error "__ARM_NEON is not defined but should be!" +#endif + +#ifdef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("arch=armv8-a+fp+simd+crypto") + +#ifndef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is not defined but should be!" +#endif + +#pragma GCC pop_options + +#ifndef __ARM_NEON +#error "__ARM_NEON is not defined but should be!" +#endif + +#ifdef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is defined but should not be!" +#endif + + +#pragma GCC pop_options + +#ifndef __ARM_FP +#error "__ARM_FP is not defined but should be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +#pragma GCC pop_options + +#ifdef __ARM_FP +#error "__ARM_FP is defined but should not be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +/* And again, but using cpu=. */ + +#pragma GCC push_options +#pragma GCC target ("cpu=cortex-a53+nofp+nosimd") +#ifdef __ARM_FEATURE_FMA +#error "__ARM_FEATURE_FMA is defined but should not be!" +#endif + +#ifdef __ARM_FP +#error "__ARM_FP is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("cpu=cortex-a53+fp+nosimd") +#ifndef __ARM_FP +#error "__ARM_FP is not defined but should be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("cpu=cortex-a53+fp+simd+nocrypto") + +#ifndef __ARM_NEON +#error "__ARM_NEON is not defined but should be!" +#endif + +#ifdef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("cpu=cortex-a53+fp+simd+crypto") + +#ifndef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is not defined but should be!" +#endif + + +#pragma GCC pop_options + +#ifndef __ARM_NEON +#error "__ARM_NEON is not defined but should be!" +#endif + +#ifdef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is defined but should not be!" +#endif + + +#pragma GCC pop_options + +#ifndef __ARM_FP +#error "__ARM_FP is not defined but should be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +#pragma GCC pop_options + +#ifdef __ARM_FP +#error "__ARM_FP is defined but should not be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +/* And again, but using just the ISA extensions. */ + +#pragma GCC push_options +#pragma GCC target ("+nofp") +#ifdef __ARM_FEATURE_FMA +#error "__ARM_FEATURE_FMA is defined but should not be!" +#endif + +#ifdef __ARM_FP +#error "__ARM_FP is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("+fp+nosimd") +#ifndef __ARM_FP +#error "__ARM_FP is not defined but should be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("+fp+simd+nocrypto") + +#ifndef __ARM_NEON +#error "__ARM_NEON is not defined but should be!" +#endif + +#ifdef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is defined but should not be!" +#endif + +#pragma GCC push_options +#pragma GCC target ("+fp+simd+crypto") + +#ifndef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is not defined but should be!" +#endif + +#pragma GCC pop_options + +#ifndef __ARM_NEON +#error "__ARM_NEON is not defined but should be!" +#endif + +#ifdef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is defined but should not be!" +#endif + + +#pragma GCC pop_options + +#ifndef __ARM_FP +#error "__ARM_FP is not defined but should be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +#pragma GCC pop_options + +#ifdef __ARM_FP +#error "__ARM_FP is defined but should not be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +/* Make sure that general-regs-only works too. */ +#pragma GCC push_options +#pragma GCC target ("general-regs-only") +#ifdef __ARM_FEATURE_FMA +#error "__ARM_FEATURE_FMA is defined but should not be!" +#endif + +#ifdef __ARM_FP +#error "__ARM_FP is defined but should not be!" +#endif + +#ifdef __ARM_NEON +#error "__ARM_NEON is defined but should not be!" +#endif + +#ifdef __ARM_FEATURE_CRYPTO +#error "__ARM_FEATURE_CRYPTO is defined but should not be!" +#endif + +#pragma GCC pop_options + +/* Also check that crc re-defines work. */ +#pragma GCC target ("+nocrc") +#ifdef __ARM_FEATURE_CRC32 +#error "__ARM_FEATURE_CRC32 is defined but should not be!" +#endif + +#pragma GCC target ("+crc") +#ifndef __ARM_FEATURE_CRC32 +#error "__ARM_FEATURE_CRC32 is not defined but should be!" +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_1.c new file mode 100644 index 00000000000..b1d52a6bbe4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_1.c @@ -0,0 +1,14 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -mcpu=thunderx -save-temps" } */ + +/* Test that cpu attribute overrides the command-line -mcpu. */ + +__attribute__ ((target ("cpu=cortex-a72.cortex-a53"))) +int +foo (int a) +{ + return a + 1; +} + +/* { dg-final { scan-assembler "//.tune cortex-a72.cortex-a53" } } */ +/* { dg-final { scan-assembler-not "thunderx" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c new file mode 100644 index 00000000000..b2c48c4524b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8-a+simd" } */ + +/* Using a SIMD intrinsic from a function tagged with nosimd should fail + due to inlining rules. */ + +#include "arm_neon.h" + +__attribute__ ((target ("+nosimd"))) +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, uint8x16_t c) +{ + return vbslq_u8 (a, b, c); /* { dg-error "called from here" } */ +} + +/* { dg-error "inlining failed in call to always_inline" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_11.c b/gcc/testsuite/gcc.target/aarch64/target_attr_11.c new file mode 100644 index 00000000000..7cfb826fc44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_11.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ + +/* Reject the negated form of non-negatable attributes. */ + +__attribute__ ((target ("no-general-regs-only"))) +int +foo (int a) +{ + return a + 1; +} + +/* { dg-error "does not allow a negated form" "" { target *-*-* } 0 } */ +/* { dg-error "is invalid" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_12.c b/gcc/testsuite/gcc.target/aarch64/target_attr_12.c new file mode 100644 index 00000000000..39cb9964003 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_12.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ + +/* Reject arguments to attributes that do not accept any. */ + +__attribute__ ((target ("general-regs-only=+crc"))) +int +foo (int a) +{ + return a + 1; +} + +/* { dg-error "does not accept an argument" "" { target *-*-* } 0 } */ +/* { dg-error "is invalid" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_13.c b/gcc/testsuite/gcc.target/aarch64/target_attr_13.c new file mode 100644 index 00000000000..0f81e9aa587 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_13.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */ + +#include "arm_acle.h" + +/* Make sure that 'crypto' is not required to compile an intrinsic + from arm_acle.h in a non-crypto function. Tests that arm_acle.h + properly clears the architectural features in its initial target + pragma. */ + +__attribute__ ((target ("+crc+nocrypto"))) +int +foo (uint32_t a, uint8_t b) +{ + return __crc32b (a, b); +} diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_14.c b/gcc/testsuite/gcc.target/aarch64/target_attr_14.c new file mode 100644 index 00000000000..a4e481d2dc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_14.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -save-temps" } */ + +/* Inlining non-strict-align functions into strict-align + functions is allowed. */ + +int +bar (int a) +{ + return a - 6; +} + +__attribute__ ((target ("strict-align"))) +int +bam (int a) +{ + return a - bar (a); +} + +/* { dg-final { scan-assembler-not "bl.*bar" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_15.c b/gcc/testsuite/gcc.target/aarch64/target_attr_15.c new file mode 100644 index 00000000000..02091c6c542 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_15.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-options "-march=armv8-a+crypto -save-temps" } */ + +/* Check that "+nothing" clears the ISA flags. */ + +__attribute__ ((target ("+nothing"))) +int +foo (int a) +{ + return a + 1; +} + +/* { dg-final { scan-assembler-not "\\+fp" } } */ +/* { dg-final { scan-assembler-not "\\+crypto" } } */ +/* { dg-final { scan-assembler-not "\\+simd" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_2.c new file mode 100644 index 00000000000..39bb6e7dd36 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_2.c @@ -0,0 +1,39 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" } */ + +/* The various ways to turn off simd availability should + turn off vectorization. */ + +__attribute__ ((target ("+nosimd"))) +int +baz (int *a) +{ + for (int i = 0; i < 1024; i++) + a[i] += 5; +} + +__attribute__ ((target ("arch=armv8-a+nosimd"))) +int +baz2 (int *a) +{ + for (int i = 0; i < 1024; i++) + a[i] += 5; +} + +__attribute__ ((target ("cpu=cortex-a53+nosimd"))) +int +baz3 (int *a) +{ + for (int i = 0; i < 1024; i++) + a[i] += 5; +} + +__attribute__ ((target ("general-regs-only"))) +int +baz4 (int *a) +{ + for (int i = 0; i < 1024; i++) + a[i] += 5; +} + +/* { dg-final { scan-tree-dump-not "vectorized 1 loops" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_3.c b/gcc/testsuite/gcc.target/aarch64/target_attr_3.c new file mode 100644 index 00000000000..50e52520ef0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */ + +/* Check that the attribute overrides the command line option + and the fix is applied once. */ + +__attribute__ ((target ("fix-cortex-a53-835769"))) +unsigned long +test (unsigned long a, double b, unsigned long c, + unsigned long d, unsigned long *e) +{ + double result; + volatile unsigned long tmp = *e; + __asm__ __volatile ("// %0, %1" + : "=w" (result) + : "0" (b) + : /* No clobbers. */); + return c * d + d; +} + +unsigned long +test2 (unsigned long a, double b, unsigned long c, + unsigned long d, unsigned long *e) +{ + double result; + volatile unsigned long tmp = *e; + __asm__ __volatile ("// %0, %1" + : "=w" (result) + : "0" (b) + : /* No clobbers. */); + return c * d + d; +} + +/* { dg-final { scan-assembler-times "between mem op and" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_4.c b/gcc/testsuite/gcc.target/aarch64/target_attr_4.c new file mode 100644 index 00000000000..d98ba42303f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_4.c @@ -0,0 +1,30 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */ + +#include "arm_acle.h" + +/* Check that enabling an ISA feature using an attribute in a file + compiled without that attribute works. */ + +__attribute__ ((target ("+crc"))) +uint32_t +foo (uint32_t a, uint8_t b) +{ + return __crc32b (a, b); +} + +__attribute__ ((target ("arch=armv8-a+crc"))) +uint32_t +fooarch (uint32_t a, uint8_t b) +{ + return __crc32b (a, b); +} + +__attribute__ ((target ("cpu=cortex-a53+crc"))) +uint32_t +foocpu (uint32_t a, uint8_t b) +{ + return __crc32b (a, b); +} + +/* { dg-final { scan-assembler-times "crc32b\tw..?, w..?, w..?\n" 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_5.c b/gcc/testsuite/gcc.target/aarch64/target_attr_5.c new file mode 100644 index 00000000000..4fc0709be81 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_5.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -save-temps" } */ + +/* Make sure that bar is inlined into bam. */ + +__attribute__ ((target ("arch=armv8-a+nocrc"))) +int +bar (int a) +{ + return a - 6; +} + +__attribute__ ((target ("cpu=cortex-a53+nocrc"))) +int +bam (int a) +{ + return a - bar (a); +} + +/* { dg-final { scan-assembler-not "bl.*bar" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_6.c b/gcc/testsuite/gcc.target/aarch64/target_attr_6.c new file mode 100644 index 00000000000..dd55a079fad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_6.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -save-temps" } */ + +/* Inlining strict-align functions into non-strict align + functions is not allowed. */ + +__attribute__ ((target ("strict-align"))) +int +bar (int a) +{ + return a - 6; +} + +int +bam (int a) +{ + return a - bar (a); +} + +/* { dg-final { scan-assembler "bl.*bar" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_7.c b/gcc/testsuite/gcc.target/aarch64/target_attr_7.c new file mode 100644 index 00000000000..32a840378ab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_7.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=thunderx -save-temps" } */ + +/* Make sure that #pragma overrides command line option and + target attribute overrides the pragma. */ + +#pragma GCC target ("cpu=xgene1") + +int +bar (int a) +{ + return a - 6; +} + +__attribute__ ((target ("tune=cortex-a53"))) +int +bam (int a) +{ + return a - bar (a); +} + +/* { dg-final { scan-assembler-times "//.tune xgene1" 1 } } */ +/* { dg-final { scan-assembler-times "//.tune cortex-a53" 1 } } */ +/* { dg-final { scan-assembler-not "thunderx" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_8.c b/gcc/testsuite/gcc.target/aarch64/target_attr_8.c new file mode 100644 index 00000000000..32d173cb25b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -save-temps" } */ + +/* bar has a subset set of the architectural flags of bam. + Inlining should be allowed. */ + +__attribute__ ((target ("arch=armv8-a+nocrc"))) +int +bar (int a) +{ + return a - 6; +} + +__attribute__ ((target ("arch=armv8-a+crc"))) +int +bam (int a) +{ + return a - bar (a); +} + + +/* { dg-final { scan-assembler-not "bl.*bar" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_9.c b/gcc/testsuite/gcc.target/aarch64/target_attr_9.c new file mode 100644 index 00000000000..3da90a152d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_9.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -save-temps" } */ + +/* bar does not have a subset of architectural flags of bam. + Inlining should be rejected. */ + +__attribute__ ((target ("arch=armv8-a+crc"))) +int +bar (int a) +{ + return a - 6; +} + +__attribute__ ((target ("arch=armv8-a+nocrc"))) +int +bam (int a) +{ + return a - bar (a); +} + + +/* { dg-final { scan-assembler "bl.*bar" } } */