From: Clifford Wolf Date: Thu, 31 Oct 2013 11:27:07 +0000 (+0100) Subject: Added placeholder check to dfflibmap and cleaned up some other placeholder checks X-Git-Tag: yosys-0.2.0~425 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0efe16f118e20e30b5fce152cf668a0929a08439;p=yosys.git Added placeholder check to dfflibmap and cleaned up some other placeholder checks --- diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 747ba17d3..e8909b91a 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -298,7 +298,7 @@ struct BlifBackend : public Backend { for (auto module_it : design->modules) { RTLIL::Module *module = module_it.second; - if ((module->get_bool_attribute("\\placeholder")) > 0) + if (module->get_bool_attribute("\\placeholder")) continue; if (module->processes.size() != 0) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0721d4fdf..583b8da9a 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -477,7 +477,7 @@ struct ShowWorker if (!design->selected_module(module->name)) continue; if (design->selected_whole_module(module->name)) { - if (module->get_bool_attribute("\\placeholder") > 0) { + if (module->get_bool_attribute("\\placeholder")) { log("Skipping placeholder module %s.\n", id2cstr(module->name)); continue; } else @@ -617,7 +617,7 @@ struct ShowPass : public Pass { if (format != "ps") { int modcount = 0; for (auto &mod_it : design->modules) { - if (mod_it.second->get_bool_attribute("\\placeholder") > 0) + if (mod_it.second->get_bool_attribute("\\placeholder")) continue; if (mod_it.second->cells.empty() && mod_it.second->connections.empty()) continue; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 111f2f919..bebf7ce63 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -498,7 +498,7 @@ struct DfflibmapPass : public Pass { logmap_all(); for (auto &it : design->modules) - if (design->selected(it.second)) + if (design->selected(it.second) && !it.second->get_bool_attribute("\\placeholder")) dfflibmap(design, it.second); cell_mappings.clear();